The goal of the eBlocks project is to empower regular people, having no programming or electronics experience, to build basic useful electronic systems around the home, office, store, etc. To achieve this goal we are creating a set of embedded system building blocks - eBlocks - that are easily connect together to build a huge variety of basic but useful monitor/controller systems. The key to our approach is to add compute intelligence to components that previously had none - to sensors, switches, light-emitting diodes (LEDs), speakers, etc. Adding compute intelligence to those items was previously cost and power prohibitive, but extremely small, cheap and low power processing devices now make such addition possible. Ideally, people could simply connect such eBlocks together to build basic systems.

Warp processors dynamically optimize their software to improve execution time and energy consumption. By performing optimizations at runtime, Warp processors have the advatanges of eliminating tool flow restrictions and extra designer effort associated with traditional compile-time optimizations. In addition, Warp processors greatly improve upon previous dynamic optimization approaches, such as BOA and Dynamo. Previous approaches utilize dynamic software optimizations, generally achieving speedups ranging from 1.1 to 1.3. By performing hardware/software partitioning at runtime, Warp processors are currently capable of achieving speedups between 2 and 4. In the near future, Warp processors are likely to achieve speedups much greater than an order of magnitude.

Warp Processors

Eblocks

This project focuses on processor and system architecture issues for Web switches.

Processor Architecture for Web Switches Processor Architectures for Web Switches

ROCCC is a C to hardware compilation project. It focuses on the acceleration of the most frequently executed code kernels in embedded applications with FPGAs as the accelerating platform. The ROCCC toolset includes two code profilers whose objectives are to identify code kernels in application programs. In its current version, ROCCC is built using the SUIF 2 framework.

Riverside Optimizing Compiler for Configurable Computing (ROCCC)

This project intends to provide security protection at the architecture level, particularly the microprocessor level. The objective is to develop a secure processor model which secure applications can easily be built on. Specifically, we want to protect user applications from being watched or even attacked through the OS, the external memory and the system buses. The secure processor design keeps the program code and data in strict confidentiality and maintains their integrity during execution. Moreover, it can protect the privacy of the processor owner through diversifying the representation of its identity.

Architectural Support for Security and Privacy Protection on Uni- and Multi- Processors

Computer Architecture and Embedded System Group

Development of new scheduling techniques for different switch organizations of an IP router that perform optimally for the Internet traffic.

Analyze the communication details between the host and the NIC to understand and model their behavior with respect to the impact of the operating system overhead.

Develops a scalable distributed software system architecture, where the major functionalities required in the Internet servers are partitioned, and resources are allocated on the basis of their needs.

Scheduling in High Performance Internet Routers

Scalable Software System for Large Internet Servers

Inteface Design for High-Performance Networking

Advanced Acceleration Solutions for Next Generation Data Center Servers

projects

This research seeks to develop an integrated research and education program on behavioral modeling, simulation, and optimization techniques to address and overcome the mixed-signal (MS) system-on-a-chip (SoC) design challenges and enable a leap to a new generation of mixed-signal VLSI systems.

Modeling, Simulation and Synthesis (optimization) for Mixed-Signal/RF/Analog Circuits

Design and Verification Methodologies for High-Performance On-chip Power Distribution Networks and Clock Networks.